FlexCAN is a highly configurable, synthesizable communication controller intellectual property (IP) block developed by NXP Semiconductors (originally introduced by Freescale Semiconductor) that implements the Controller Area Network (CAN) protocol. It supports the CAN 2.0A/B specifications, the CAN with Flexible Data-rate (CAN FD) extension, and is compliant with ISO 11898-1.
Overview
FlexCAN serves as a dedicated hardware peripheral enabling serial bus communication in embedded systems, with particular emphasis on automotive networking, industrial automation, and real-time control applications. It provides multi-master, broadcast-oriented message transmission over a two-wire differential bus (CAN_H and CAN_L), incorporating hardware-level error detection, non-destructive arbitration, and fault confinement mechanisms.
The module originated in the early 2000s within Freescale Semiconductor's microcontroller and processor families. It was first integrated into the MPC5500 family of 32-bit Power Architecture microcontrollers (2003) and received significant enhancements in the MPC5510 family (2007). Following the merger of Freescale with NXP Semiconductors in December 2015, FlexCAN was maintained and expanded across NXP's broader product portfolio.
Architecture
FlexCAN's internal architecture centers on a dedicated Protocol Engine that implements the core CAN protocol logic, including frame arbitration, bit stuffing/de-stuffing, and error detection. Key structural components include:
- Mailboxes (Message Buffers): Configurable receive and transmit buffers, typically ranging from 16 to 128 per instance depending on the device. Each mailbox contains control/status fields, an identifier field, and data payload space. Mailboxes support individual receive mask registers for precise message filtering.
- Receive FIFO: An optional buffering mechanism that stores received frames in arrival order, with programmable ID filter elements for selective acceptance.
- Protocol Engine: Handles bit-level protocol operations including synchronization, arbitration, and error frame generation.
- Host interface: Connects the module to the system bus (typically AHB or APB) for memory-mapped register access and DMA transfers.
Key Features
- Flexible message buffering: Up to 128 mailboxes with individual masking for fine-grained message filtering.
- CAN FD support: Extends data payload from 8 to 64 bytes and enables higher data-phase bit rates (up to 8 Mbps), improving throughput for bandwidth-intensive applications.
- Error management: Implements the standard CAN error detection and fault-confinement mechanisms, including bit, stuff, CRC, form, and acknowledgment error detection, along with automatic retransmission and bus-off recovery.
- Pretended Networking mode: Allows low-power monitoring of the CAN bus with selective wake-up on matching frames, useful for power-constrained automotive nodes.
- Loop-back mode: Enables self-testing by internally routing transmitted messages back to the receiver without external hardware.
- 16-bit timestamping timer: Provides message ordering and synchronization across the network.
- Configurable transmission priority: Supports lowest-buffer-number, lowest-ID, or local-priority arbitration schemes.
Configuration and Bit Timing
FlexCAN bit timing is configurable through a prescaler and segment parameters (propagation, phase segment 1, phase segment 2, and synchronization segments). The nominal bit rate in classical CAN mode is limited to 1 Mbps per ISO 11898-1. CAN FD operation allows a separate, higher bit rate during the data phase. Clock sources are selectable, with external crystals typically recommended for precision timing requirements.
Applications
FlexCAN is widely deployed in automotive electronic control units (ECUs), including powertrain systems, body control modules, infotainment systems, and advanced driver-assistance systems (ADAS). It is also used in industrial automation for sensor/actuator networks, programmable logic controllers, and robotics, often integrating with higher-layer protocols such as CANopen. The module is present across NXP product lines including the S32K automotive series, i.MX crossover processors, Kinetis families, and Layerscape processors.
Integration
FlexCAN is supported by NXP's MCUXpresso SDK through dedicated peripheral drivers, and by the Linux kernel via the CONFIG_CAN_FLEXCAN driver for SocketCAN support. The IP is also available for licensing, with deliverables including Verilog RTL source code, testbenches, and documentation.
