Salter (trap)

In digital circuit design, a Salter trap is a type of latch used to capture and hold a specific value. It is primarily employed in asynchronous systems or at asynchronous interfaces of synchronous circuits. The Salter trap is distinguished by its sensitivity to metastable states and its role in preventing or mitigating the propagation of these unstable states into the broader system.

The fundamental function of a Salter trap is to capture a signal at a particular point in time and hold that value for a specified duration. Unlike a standard D-latch or flip-flop that might resolve to either a high or low state randomly when presented with a metastable input, a Salter trap is designed with components and feedback mechanisms that attempt to quickly resolve the metastability to a predetermined, often a safe, state. This often involves forcing the output to a known inactive level.

The operation typically involves a race condition between transistor pairs that determines the final output value. While the trap cannot entirely eliminate metastability, it significantly reduces the probability and duration of the metastable state, thus limiting its impact on subsequent logic stages. The trapped value is often held until a reset or enable signal allows a new input to be captured.

Key characteristics of a Salter trap include:

• Metastability Handling: Designed to minimize the impact of metastable states by resolving to a defined output state.
• Asynchronous Operation: Commonly used in circuits that lack a global clock signal.
• Pulse-Based Operation: Typically triggered by a pulse, capturing the input value at the pulse's leading or trailing edge.
• Temporary Storage: The captured value is held for a finite period, often determined by circuit parameters or a reset signal.

The name "Salter trap" is sometimes used generically to refer to any type of circuit attempting to capture asynchronous signals and mitigate metastability, although designs can vary significantly. Proper implementation requires careful consideration of timing margins, transistor sizing, and process variations to ensure reliable operation.