Definition
The planar process is a semiconductor fabrication technique that produces flat, chemically uniform surfaces on silicon wafers to enable precise photolithographic patterning of integrated circuits. By oxidizing silicon to form a protective silicon dioxide layer and using successive steps of oxidation, diffusion, deposition, and etching, the process maintains a planar (flat) topology throughout device construction.
Overview
Developed in the late 1950s and early 1960s, the planar process supplanted earlier, non‑planar methods that suffered from surface irregularities and limited pattern resolution. The technique made it possible to fabricate transistors, diodes, and later complex integrated circuits (ICs) with high yield and reliability. Its introduction is widely regarded as a pivotal advance that enabled the rapid scaling of semiconductor technology, ultimately leading to the modern computer age.
Key stages typically include:
- Thermal Oxidation – Growth of a silicon dioxide (SiO₂) layer on a cleaned silicon wafer, providing both a protective mask and a high‑quality insulating surface.
- Photolithography – Application of a photoresist, exposure through a patterned mask, and development to define regions for subsequent processing.
- Diffusion or Ion Implantation – Introduction of dopant atoms (e.g., phosphorus, boron) into exposed silicon regions to form n‑type or p‑type zones.
- Etching – Selective removal of silicon dioxide or doped silicon, often using wet or plasma etchants, to create the desired device geometry while preserving planar continuity.
- Deposition – Application of thin films (metals, polysilicon, dielectrics) by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other methods, followed by planarization steps such as chemical‑mechanical polishing (CMP) to restore flatness.
The planar process enabled the mass production of reliable, high‑density ICs and remains a foundational methodology in contemporary microelectronics, albeit augmented with advanced lithography (e.g., extreme ultraviolet) and three‑dimensional (3‑D) integration techniques.
Etymology/Origin
The term “planar” derives from the Latin planus, meaning “flat” or “level.” The phrase “planar process” was coined to emphasize the method’s focus on maintaining a flat surface throughout fabrication. The technique is credited primarily to Jean Hoerni of Fairchild Semiconductor, who published the concept in 1959. Parallel developments by other researchers, notably Kurt Lehovec and Robert N. Noyce, contributed to the broader adoption of planar technology.
Characteristics
| Characteristic | Description |
|---|---|
| Surface Uniformity | Produces a continuous, smooth oxide layer that serves as a robust mask and electrical insulator. |
| Scalability | Compatible with successive lithographic layers, allowing progressive miniaturization of device features. |
| Yield Improvement | Reduces defect density caused by surface topography, increasing functional chip yield. |
| Process Integration | Forms the basis for subsequent steps such as field‑effect transistor (FET) formation, metallization, and interconnect layering. |
| Thermal Stability | Silicon dioxide’s high melting point and chemical inertness permit high‑temperature processing without degradation. |
Related Topics
- Photolithography – The optical patterning technique essential to defining circuit layouts on planarized wafers.
- Silicon Dioxide (SiO₂) Gate Oxide – The insulating layer created during the oxidation step of the planar process.
- Chemical‑Mechanical Polishing (CMP) – A planarization method used after deposition to restore surface flatness.
- Integrated Circuit (IC) Fabrication – The broader manufacturing discipline that incorporates the planar process as a core component.
- Moore’s Law – The observation of exponential growth in transistor count, facilitated by planar process advancements.
- Three‑Dimensional (3‑D) Integration – Emerging technologies that stack multiple planar layers to increase device density while building on planar processing fundamentals.