Gate array

Definition
A gate array is a type of Application‑Specific Integrated Circuit (ASIC) in which a prefabricated wafer contains a regular matrix of uncommitted transistors or logic gates. The final functionality of the device is defined by customizing the interconnect layers—typically metal and sometimes polysilicon—added after the wafer has been manufactured. This approach allows designers to achieve a balance between the low non‑recurring engineering (NRE) costs of standard cell or programmable logic devices and the high performance of full custom ASICs.

Historical development
Gate arrays emerged in the early 1970s as a response to the high cost and long lead times associated with full custom chip design. Companies such as Fairchild Semiconductor and National Semiconductor introduced gate‑array products to provide faster time‑to‑market for medium‑volume electronic products. Throughout the 1980s and early 1990s, gate arrays were widely used in telecommunications, consumer electronics, and computer peripherals. The rise of field‑programmable gate arrays (FPGAs) and the increasing sophistication of full‑custom CMOS processes led to a decline in gate‑array popularity by the late 1990s, although the concept persists in modern “structured ASIC” and “standard‑cell” design methodologies.

Technology and manufacturing process

1. Base wafer fabrication – A semiconductor foundry fabricates a wafer that contains a dense, regular array of identical logic cells (e.g., NAND, NOR, flip‑flops) with all transistors fully formed but without dedicated interconnects.
2. Design specification – The customer creates a netlist that describes the desired circuit functionality and maps it onto the available logic cells.
3. Mask creation – One or more custom photomasks are produced for the metallization steps (typically two to five metal layers). These masks define the specific wiring that connects the pre‑existing logic cells.
4. Metal layer deposition – The wafer undergoes successive photolithography, etching, and metal deposition steps using the custom masks. This step implements the circuit’s interconnect topology.
5. Testing and packaging – Completed dies are tested for functional correctness, sorted, and packaged for integration into electronic systems.

Advantages

• Reduced NRE cost compared with full‑custom ASICs because the majority of the silicon (the transistor array) is shared across many designs.
• Shorter development cycle; only the metal layers require custom masks, which can be produced more quickly than full lithographic layers.
• Predictable electrical characteristics, as the base transistors are fabricated in a mature, high‑yield process.

Disadvantages

• Lower density and performance relative to full‑custom designs, due to the fixed placement of logic cells that may not be optimal for a particular circuit.
• Limited flexibility in implementing analog or mixed‑signal functions, which often require custom transistor layouts.
• The approach is less competitive in applications where high volumes justify the cost of a fully custom ASIC or where reconfigurability is needed (e.g., using FPGAs).

Typical applications

• Telecommunications equipment (e.g., line interface cards, protocol converters).
• Consumer electronic peripherals such as modems and printer controllers.
• Industrial control systems where moderate production volumes and moderate performance requirements are acceptable.

Related concepts

• Standard‑cell ASIC – Uses a library of pre‑designed, characterized cells placed and routed by automated tools; all layers are custom.
• Field‑Programmable Gate Array (FPGA) – Provides post‑fabrication configurability via a matrix of programmable logic blocks and interconnect.
• Structured ASIC – A hybrid approach that combines a pre‑fabricated base with limited custom routing, intended to improve upon traditional gate‑array density and performance.

References

1. R. R. Anderson, "Gate‑Array ASICs: Design and Fabrication," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 5, no. 3, 1986.
2. J. R. Wolfe, ASIC Design Methodology, Springer, 1994, Chapter 7.
3. M. S. S. R. Srinivasan, "From Gate Arrays to Structured ASICs," Proceedings of the 2004 International Symposium on VLSI Design, 2004.