The 3 nm process is a semiconductor manufacturing technology node that follows the 5 nm node. In the semiconductor industry, "3 nm" is primarily a commercial or marketing designation used by individual chip manufacturers (foundries) to refer to a new generation of improved silicon chips, rather than a precise physical measurement of any transistor feature. According to the International Roadmap for Devices and Systems (2021), a "3 nm" node is expected to have a contacted gate pitch of approximately 48 nanometers and a tightest metal pitch of approximately 24 nanometers.
Key Manufacturers and Approaches
TSMC (Taiwan Semiconductor Manufacturing Company) began volume production of its 3 nm FinFET process (N3) in the fourth quarter of 2022. TSMC's N3 technology offers up to 1.6× logic density gain and 30–35% power reduction at the same speed compared to its 5 nm (N5) process. TSMC has since introduced several variants including N3E (enhanced), N3P (performance-optimized), N3X (high-performance), and N3C (cost-optimized). TSMC's 3 nm nodes continue to use FinFET transistor architecture.
Samsung started initial production of its 3 nm process using Gate-All-Around (GAA) transistor architecture (branded MBCFET) in mid-2022, becoming the first foundry to commercialize GAA technology. Samsung's first-generation 3 nm process (3GAE/SF3E) claims up to 45% power reduction, 23% performance improvement, and 16% area reduction compared to its 5 nm process. A second-generation 3 nm process (3GAP/SF3) targets further improvements.
Intel developed its "Intel 3" process (without the "nm" suffix), a refined FinFET technology that entered high-volume production in 2024. Intel 3 uses enhanced EUV lithography and offers improved performance per watt compared to Intel 4.
Transistor Architectures
Samsung's 3 nm process uses GAAFET (Gate-All-Around Field-Effect Transistor) technology, specifically its MBCFET (Multi-Bridge-Channel FET) variant, where the gate surrounds the transistor channel on all four sides. TSMC's 3 nm process continues to use FinFET (Fin Field-Effect Transistor) technology, where the gate wraps around the channel on three sides. Intel's Intel 3 also uses FinFET technology.
Technical Specifications (Selected Nodes)
| Parameter | TSMC N3 (N3B) | TSMC N3E | Samsung SF3E | Intel 3 |
|---|---|---|---|---|
| Transistor type | FinFET | FinFET | MBCFET (GAA) | FinFET |
| Transistor density (MTr/mm²) | ~197 | ~216 | ~150 | ~143 |
| Contacted gate pitch (nm) | 45 | 48 | 40 | 50 |
| Minimum metal pitch (nm) | — | 23 | 32 | 30 |
| SRAM bit-cell size (μm²) | 0.0199 | 0.021 | — | 0.024 |
Commercial Products
Notable commercial chips manufactured on 3 nm processes include Apple's A17 Pro, M3, M4, and their variants (TSMC N3B/N3E); Qualcomm's Snapdragon 8 Elite (TSMC N3E); MediaTek's Dimensity 9400 (TSMC N3E); and Xiaomi's XRING O1 (TSMC N3E). Samsung's 3 nm GAA process has been identified in cryptocurrency mining ASICs.
Historical Context
In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm. In 2006, researchers at KAIST developed a 3 nm width multi-gate MOSFET based on GAAFET technology, then the world's smallest nanoelectronic device. Commercial 3 nm production began approximately two decades later, in 2022.
