The 3 nm process (also written 3 nm or 3‑nm) is a semiconductor manufacturing technology node characterized by a nominal minimum gate length of approximately three nanometres. It represents a continuation of the industry’s trend toward smaller feature sizes, enabling higher transistor density, improved performance, and reduced power consumption relative to preceding nodes such as 5 nm.
Overview
The 3 nm node is part of the advanced logic process families used for central‑processing units (CPUs), graphics‑processing units (GPUs), system‑on‑chip (SoC) devices, and other high‑performance integrated circuits. The designation “3 nm” does not correspond to a single physical dimension; rather, it is a marketing term that reflects a combination of design rules, transistor architecture, and lithographic capability. Typical attributes of the 3 nm node include:
- Transistor density: Approximately 300–350 million transistors per square millimetre, representing a 1.5–2× increase over 5 nm.
- Performance: For a given voltage, 3 nm transistors can deliver 10–15 % higher speed, or alternatively operate at lower voltage for equivalent speed, yielding power savings.
- Power efficiency: Reported reductions of 30 % or more in dynamic power consumption compared with 5 nm, depending on circuit design and operating conditions.
Key Technology Features
- Gate‑All‑Around (GAA) Nanowire/FinFET structures – Unlike the FinFETs used at 5 nm, many 3 nm implementations adopt GAA transistors, where the channel is wrapped by the gate material on all sides, improving electrostatic control.
- Extreme Ultraviolet (EUV) Lithography – Multi‑patterning EUV lithography is employed for the most critical layers, reducing the number of mask steps compared with deep‑ultraviolet (DUV) multi‑patterning used at earlier nodes.
- High‑κ/Metal‑gate (HKMG) stack – Advanced dielectric and metal gate materials are used to maintain low leakage currents at the reduced dimensions.
- Self‑aligned contact (SAC) and advanced via schemes – To mitigate resistance and capacitance penalties associated with finer pitches.
Commercial Development and Production
- TSMC – Taiwan Semiconductor Manufacturing Company (TSMC) announced mass production of its 3 nm process (designated N3) in early 2022, with first‑tier customers such as Apple (A17 Bionic) and NVIDIA (H100 “Blackwell”) qualifying chips in 2023. TSMC’s N3 platform includes both N3 (full GAA) and N3E (enhanced FinFET) options.
- Samsung – Samsung Electronics launched its 3 nm GAA process (referred to as “3 nm GAA” or “3 nm class”) in 2022, employing a vertically stacked nanosheet architecture. Early products include the Exynos 2400 mobile SoC and various high‑performance computing (HPC) accelerators.
- Intel – Intel announced plans for a 3 nm “process‑node” under its “Intel 4” (formerly 7 nm) roadmap, with production slated for 2024. Intel’s approach utilizes a refined FinFET architecture rather than GAA.
Applications
The 3 nm node is targeted at applications that demand maximal performance per watt, such as:
- Mobile smartphones and tablets
- High‑end graphics and gaming consoles
- Data‑center accelerators and AI inference chips
- Network infrastructure processors
Challenges
Scaling to 3 nm presents several technical and economic challenges:
- Lithography limits – EUV source power and mask defectivity become increasingly critical.
- Variability and yield – As dimensions shrink, stochastic effects in dopant placement and line‑edge roughness can impact device uniformity.
- Cost – Capital expenditure for 3 nm fabs exceeds $15 billion, and per‑wafer costs are substantially higher than at earlier nodes.
Future Outlook
The 3 nm process is expected to serve as the leading technology for high‑performance products through the mid‑2020s. Subsequent nodes (e.g., 2 nm and beyond) are under research, focusing on further transistor architecture innovations such as nanosheet GAA, monolayer materials, and alternative channel materials (e.g., germanium, III‑V compounds).
References
- TSMC, “TSMC Announces 3nm (N3) Production – First Mass Production of 3nm Technology,” Press release, 2022.
- Samsung Electronics, “Samsung Introduces 3nm GAA Process Technology,” News release, 2022.
- Intel Corporation, “Intel 4 Manufacturing Roadmap,” Investor Presentation, 2023.
- International Technology Roadmap for Semiconductors (ITRS), “FinFET and GAA Scaling,” 2021.
Note: All information presented reflects publicly available data from reputable semiconductor manufacturers and industry roadmaps as of 2024.